1. Field of the Invention
This invention relates to a memory array with improved addressing. More particularly, this invention relates to such a memory array in which an improved addressing scheme allows substantial reduction in memory accessing time. Most especially, this invention relates to a bipolar integrated circuit memory array in which a plurality of columns in the memory array are addressed for reading out information simultaneously, and in which a novel addressing scheme is used to reduce the access time for reading out information from the memory array.
2. Description of the Prior Art
Static bipolar integrated circuit memory arrays are well known in the art. For example, 4K.times.1-bit random access memories designated by product numbers 93470 and 93471 and fabricated using the Isoplanar process by Fairchild Camera and Instrument Corporation, Mountain View, California, have achieved substantial success in the market place. These memories are described by Herndon, Ho and Ramirez, "Static Bipolar Memory Chips Keep Shrinking", Fairchild Journal of Semiconductor Progress, Volume 5, Number 4, pages 16-18 (July-August 1977).
These memories are arranged in rows and columns, and a selected row and column are addressed substantially simultaneously in order to read information out of the memory array. This approach works well for a 4K.times.1 organization of the array, in which one bit of information is read out at a time. However, if it is desired to organize such memory array so that more than one column of information is read out simultaneously, for example, a 1K or 2K.times.8 organization, addressing the columns at the same time as the rows results in a substantial decrease in the rate of change of the row voltage, thus increasing the time it takes a row to reach a proper level for a read operation. Such a delay can easily double the time required for reading information out of the memory. As memory integrated circuit designers adapt the above memory arrays to different organizations, a need therefore exists for an improved scheme for addressing the memory arrays so that their access time can be reduced.